Technical Publications

Issued US Patents

I am a named inventor on the following patents. All these patents are assigned to Xilinx Inc.

  1. "Register Protection Structure for FPGA", US5600597
  2. "Circuit for simultaneously inputting and outputting signals on a single wire", US5612633
  3. "High speed mask register for a configurable cellular array", US 5670897
  4. "FPGA with parallel and serial user interfaces", US5737235
  5. "Configurable Cellular Array", US5491353
  6. "Wildcard addressing structure for configurable cellular array", US 5500609
  7. "Mask register for a configurable cellular array", US5552722
  8. "Register with duplicate decoders for configurable cellular array", US5528176
  9. "Hierarchically connectable configurable cellular array", US 5469003
  10. "Configurable cellular array", US 5243238
  11. "Programmable Switch for FPGA input/output signals", US5705938
  12. "Routing Resources for hierarchical FPGA", US5701091

Papers

  1. "Configurable Logic: A Dynamically Programmable Cellular Architecture and its VLSI Implementation", PhD Thesis CST62-89, University of Edinburgh, Dept. Computer Science.
  2. "Configurable Hardware, A New Paradigm for Computation'', Advanced Research in VLSI, Proc. 1989 Decennial Caltech Conference, MIT Press.
  3. "Configurable Hardware: Two Case Studies of Micro-Grain Computation'', Proc. International Conference on Systolic Arrays, Killarney 1989, Prentice Hall.
  4. "Configurable Hardware: Two Case Studies of Micro-Grain Computation'', Journal of VLSI Signal Processing 2, 9-16, Kluwer Academic Publishers. (expanded version of previous conference paper).
  5. "A Novel Implementation Style for Teaching VLSI'', Proc. 1989 VLSI Education Conference, Santa Clara, July 1989.
  6. "Image Pattern Recognition using Configurable Logic Cell Arrays'', Proc. Computer Graphics International, Leeds 1989. Published by Springer-Verlag.
  7. "Implementation of Configurable Hardware using Wafer Scale Integration'', Proc. International Conference on Wafer Scale Integration 1990.
  8. "Bipolar CAL Chip Doubles Speed of FPGA's'', Proc. Oxford 1991 International Workshop on FPGA's, Abingdon EE &CS Books England.
  9. "The Use of FPGA's in a Novel Computing Subsystem'', Proc. FPGA 1992 First International ACM Workshop on Field Programmable Gate Arrays, Berkeley CA.
  10. ``Using CAL to Accelerate Maze Routing of CAL Designs'', Field Programmable Logic and Applications, Proc. 2nd International Workshop. Vienna, Austria 1992.
  11. Chapter 3 and sections of chapter 6 in " Field Programmable Gate Arrays", John V. Oldfield and Richard C. Dorf, John Wiley 1995.
  12. "XC6200 Fastmap Processor Interface", Field Programmable Logic and Applications, Proc. 5th International Workshop. Oxford, 1995. Springer LNCS 975.
  13. "A Fast Constant Coefficient Multiplier for the XC6200", Field Programmable Logic and Applications, Proc. 6th International Workshop. Darmstadt, 1996. Springer LNCS.
  14. "An 800Mpixel/sec Reconfigurable Image Correlator on XC6216", Field Programmable Logic and Applications, Proc. 7th International Workshop. London, 1997. Springer LNCS 1304.
  15. "Reconfigurable Computing and the Xilinx XC6200", Invited Tutorial Paper, VLSI97, Gramado, Brazil 1997.
  16. "DES Key Breaking, Encryption and Decryption on the XC6216", Proceedings IEEE Symposium on Field Programmable Custom Computing Machines (FCCM), Napa CA, 1998.

Video

"Reconfigurable Processing: The Third Computing Paradigm", Number 12, The Distinguished Lecture Series, University Video Communications, 1996.

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