Technical Papers

1.       "Configurable Logic: A Dynamically Programmable Cellular Architecture and its VLSI Implementation", PhD  Thesis CST62-89, University of Edinburgh , Dept. Computer Science. [Thesis (PDF 19.3Mb), Colour Illustrations (PDF 15Mb)]

2.       "Configurable Hardware, A New Paradigm for Computation'', Advanced Research in VLSI, Proc. 1989   Decennial Caltech Conference, MIT Press. [download PDF 926kB]

3.       "Configurable Hardware: Two Case Studies of Micro-Grain Computation'', Proc. International Conference on  Systolic Arrays, Killarney 1989, Prentice Hall. [download PDF 465kB]

4.       "Configurable Hardware: Two Case Studies of Micro-Grain Computation'', Journal of VLSI Signal   Processing 2, 9-16, Kluwer Academic Publishers. 

5.       "A Novel Implementation Style for Teaching VLSI'', Proc. 1989 VLSI Education Conference, Santa Clara ,   July 1989. [download PDF 1.3MB]

6.       "Image Pattern Recognition using Configurable Logic Cell Arrays'', Proc. Computer Graphics International,    Leeds 1989. Published by Springer-Verlag. [download PDF 1.6MB]

7.       "Implementation of Configurable Hardware using Wafer Scale Integration'', Proc. International Conference on  Wafer Scale Integration 1990.

8.       "Bipolar CAL Chip Doubles Speed of FPGA's'', Proc. Oxford 1991 International Workshop on FPGA's,  Abingdon EE & CS Books England .

9.       "The Use of FPGA's in a Novel Computing Subsystem'', Proc. FPGA 1992 First International ACM  Workshop on Field Programmable Gate Arrays, Berkeley CA . [download PDF 1MB]

10.   "Using CAL to Accelerate Maze Routing of CAL Designs'', Field Programmable Logic and Applications,   Proc. 2nd International Workshop. Vienna , Austria 1992. [download PDF 468kB]

11.   Chapter 3 and sections of chapter 6 in " Field Programmable Gate Arrays", John V. Oldfield and Richard C. Dorf, John Wiley 1995.

12.   "XC6200 Fastmap Processor Interface", Field Programmable Logic and Applications, Proc. 5th International  Workshop. Oxford , 1995. Springer LNCS 975.

13.   "A Fast Constant Coefficient Multiplier for the XC6200", Field Programmable Logic and Applications, Proc.  6th International Workshop. Darmstadt , 1996. Springer LNCS. [download PDF 33.4kB]. Copyright Notice: © 1996 Springer-Verlag.

14.   "An 800Mpixel/sec Reconfigurable Image Correlator on XC6216", Field Programmable Logic and   Applications, Proc. 7th International Workshop. London , 1997. Springer LNCS 1304.

15.   "Reconfigurable Computing and the Xilinx XC6200", Invited Tutorial Paper, VLSI97, Gramado , Brazil 1997.

16.   "DES Key Breaking, Encryption and Decryption on the XC6216", Proceedings IEEE Symposium on Field  Programmable Custom Computing Machines (FCCM), Napa CA , 1998.

17.  "Soft RF: new frontier for hackers", EE Times, issue 1074, August 16, 1999 .

18.  "Its FPL Jim - But not as we know it!  Opportunities for the new commercial architectures", Invited Keynote Talk, Field Programmable Logic and Applications, Proc. 10^th International Workshop, Villach , 2000. Springer LNCS 1896. [download PDF 86.3kB]. Copyright Notice: © 2000 Springer-Verlag.

19.  "The Third Wave is Hitting the Beach", Comment Article, Electronic Business, October 2000. Online version.

20.  "Secure Configuration of a Field Programmable Gate Array", Proceedings IEEE Symposium on Field  Programmable Custom Computing Machines (FCCM), Rohnert Park CA , 2001. [download PDF 34.8kB]. Copyright Notice: © 2001 IEEE.

21.  "Secure Configuration of Field Programmable Gate Arrays", Programmable Logic and   Applications, Proc. 11th International Workshop. Belfast , 2001. Springer LNCS 2147. [download PDF 40.7kB]. Copyright Notice: © 2001 Springer-Verlag.

22.  "A Reconfigurable Embedded Input Device for Kinetically Challenged  Persons",  Proc. 11th International Workshop. Belfast , 2001. Springer LNCS 2147

23.  "Parameterized hardware libraries for configurable system-on-chip technology", Canadian Journal Electrical and Computer Engineering, Vol. 26, No. 3/4, July/October 2001.

24.  "Cryptographic Rights Management of FPGA Intellectual Property Cores", Proceedings Tenth ACM International Symposium on FPGAs.  Monterey CA , 2002. [download PDF 40.7kB]. Copyright Notice: © ACM, 2002. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in Proceedings Tenth ACM International Symposium on FPGAs 2002, http://doi.acm.org/10.1145/503048.503065.

25.  "Cryptographically Enforced Pay-Per-Use Licensing of FPGA Design Intellectual Property", Proceedings IP Based Design 2002.  Grenoble, France, 2002. [download PDF 23.9kB, PowerPoint Slides on conference website]

26.  "Validation of an Advanced Encryption Standard (AES) IP Core", Proceedings IEEE Symposium on Field  Programmable Custom Computing Machines (FCCM), Napa CA , 2004. [download PDF 24.0kB]. Copyright Notice: © 2004 IEEE.

UK Patents

The following patents are assigned to Algotronix Ltd.

1.     "Method of Protecting Intellectual Property Cores on Field Programmable Gate Array", Publication No. US 2002/0199110 [download PDF 1.3MB]

2.     "Method of Using a Mask Programmed Key to Securely Configure a Field Programmable Gate Array",  Publication No. US 2001/0037458 [download PDF 1.4MB]

3.    "Method and Apparatus for Secure Configuration of a Field Programmable Gate Array",  Publication No. US 2001/0015919   [download PDF 2.2MB]

Issued US Patents

The following patents are assigned to Dr. Kean's previous employer, Xilinx Inc.. 

1.      "Configurable cellular array", US Patent 5,243,238

2.     "Hierarchically connectable configurable cellular array", US Patent 5,469,003

3.       "Configurable cellular array", US Patent 5,491,353

4.       "Wildcard addressing structure for configurable cellular array", US Patent 5,500,609

5.       "Register with duplicate decoders for configurable cellular array", US Patent 5,528,176

6.     "Mask register for a configurable cellular array", US Patent 5,552,722

7.     "Register Protection Structure for FPGA", US Patent 5,600,597

8.      "Circuit for simultaneously inputting and outputting signals on a single wire", US Patent 5,612,633

9.      "High speed mask register for a configurable cellular array", US Patent 5,670,897

10.   "Routing Resources for hierarchical FPGA", US Patent 5,701,091

11.   "FPGA with parallel and serial user interfaces", US Patent 5,737,235

12.  "Match Register with Duplicate Decoders",  U.S. Patent 5,798,656

13.  "Embedded memory for field programmable gate array", US Patent 5,801,547

14.  "Function unit for fine-grained FPGA", US Patent 5,831,448

15.  "Hierarchically Connectable Configurable Cellular Array",  U.S. Patent 5,861,761

16.  "FPGA using RAM control signal lines as routing or logic resources after configuration", US Patent 5,909,125

17.  "FPGA using RAM control signal lines as routing or logic resources after configuration", US Patent 6,157,211

18.  "Programmable Switch for FPGA input/output signals", US Patent 5,705,938 re-issued as US RE 37,195

19.  "Configurable cellular array", US Patent 6,292,018

20.  "FPGA using RAM control signal lines as routing or logic resources after configuration", US Patent 6,304,103